This invention relates to capacitors formed on electronic devices and more particularly to capacitors formed between interconnection wiring layers on semiconductor chips to form integrated circuits.
Various approaches have been tried to form parallel plate capacitors in interconnection wiring by using the metal of two adjacent wiring layers and the interlevel dielectric material between. Another approach has been to form capacitors between the substrate typically of silicon, a dielectric of thermal oxide and a top electrode of poly-silicon or metal. These capacitors are especially suited for substrate decoupling capacitors and may be fabricated in the front-end of the line processing.
In the field of analog and mixed signal design, capacitors are required as a passive element in the design of bandpass filters. Analog and mixed signal circuits are designed to operate at higher frequencies than decoupling capacitors to service the wireless communications markets. Decoupling capacitors formed over the substrate or close thereto suffer from capacitive losses to the substrate, resulting in poor bandpass filter operation.
Another problem in forming a stack capacitor in the interconnection wiring layers is that if the capacitor plates are etched at one time by reactive ion etching (RIE) a debris is deposited on the dielectric on the sidewall between the parallel plates causing shorting between the plates.
Another problem has been that when the capacitor plates are not planar and parallel to one another, the capacitor value varies.
It is therefore desirable to form capacitors in the interconnection wiring that are physically isolated from the substrate.
It is further desirable to form capacitors in the interconnection wiring that are inherently reliable via a manufacturing method.
It is further desirable to form capacitors in the interconnection wiring of a semiconductor chip with clean dielectric to dielectric interfaces, free of debris from processing, between the capacitor dielectric and the interlevel wiring dielectric to prevent high leakage currents and shorts and to provide very low leakage currents.
An interconnection wiring system containing at least one capacitor is described comprising a substrate having a planar upper surface of insulating and conductive regions therein, a first level of interconnection wiring thereover interconnecting the conductive regions, the first level of interconnection wiring further including a patterned region to form the lower electrode of a capacitor, a first dielectric layer formed over the lower electrode, a top electrode formed over the first dielectric layer to form the top electrode of the capacitor, the top electrode having a perimeter interior to the perimeter of the first dielectric layer, a second dielectric layer formed over the first level of interconnection wiring over the first dielectric layer and over the top electrode, the second dielectric layer being substantially thicker than the first level of interconnection wiring, the first dielectric layer and the top electrode, the second dielectric layer having an upper surface and having vias therein filled with conductive material to the upper surface, the vias being in contact with regions of the first level of interconnection wiring and the top electrode, and a second level of interconnection wiring interconnecting the vias.
The invention further provides an interconnection wiring system containing at least one capacitor comprising a substrate having a planar upper surface of insulating and conductive regions therein, a first level of interconnection wiring thereover interconnecting the conductive regions, a first dielectric layer formed over the first level of interconnection wiring, the first dielectric layer having an upper surface and having vias filled with conductive material to the upper surface and in contact with regions of the first level of interconnection wiring, at least one the vias having a patterned region to form the lower electrode of a capacitor, a second dielectric layer formed over the lower electrode and extending beyond the perimeter of the lower electrode, and a second level of interconnection wiring interconnecting the vias filed with conductive material and formed over the second dielectric layer to form the top electrode of the capacitor.